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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//      SignalValidationDelay
//////////////////////////////////////////////////////////////////////////////////
module Signalvalidationdelay#
(
    
    parameter   VALUE         = 1, 
                //% Counter Total Bits<br>
    parameter   TOTAL_BITS    = 4, 
                //% Counter Maximun value<br>
    parameter   MAX_COUNT     = 4'd10, 
                //% Signal Polarity<br>
    parameter   POL           = 1'b1
)
(
                                    //% Clock Input<br>
    input                           i_Clk,
                                    //% Asynchronous Reset Input<br>
    input                           i_Rst,
                                    //% Clock Enable<br>
    input                           i_CE,
                                    //% Counter Maximun Value<br>
    input   [(TOTAL_BITS - 1):0]    i_vMaxCnt,
                                    //% Start<br>
    input                           i_Start,
                                    //% Done<br>
    output                          o_Done
);
//////////////////////////////////////////////////////////////////////////////////
// Includes
//////////////////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////////////////
// Defines
//////////////////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////////////////
// Internal Signals
//////////////////////////////////////////////////////////////////////////////////

reg                     rDone_d;
reg                     rDone_q;

reg [(TOTAL_BITS-1):0]  rvCounter_d;
reg [(TOTAL_BITS-1):0]  rvCounter_q;

wire wRst;

assign wRst = i_Rst | (i_Start ^ VALUE);
//////////////////////////////////////////////////////////////////////////////////
// Continous assigments
//////////////////////////////////////////////////////////////////////////////////
assign    o_Done = rDone_q;
//////////////////////////////////////////////////////////////////////////////////
// Sequential logic
//////////////////////////////////////////////////////////////////////////////////
always @(posedge i_Clk or posedge wRst) 
begin
    if (wRst)
    begin
        rDone_q    <=  ~POL;
        rvCounter_q <= {TOTAL_BITS{1'b0}};
    end
    else
    begin
        if(i_CE)
        begin
            rvCounter_q <= rvCounter_d;
            rDone_q     <= rDone_d;
        end
        else
        begin
            rvCounter_q <= rvCounter_q;
            rDone_q     <= rDone_q;
        end
    end
end
//////////////////////////////////////////////////////////////////////////////////
// Combinational logic
//////////////////////////////////////////////////////////////////////////////////
always @* 
begin
    rDone_d =   ~POL;
    rvCounter_d =   rvCounter_q;
    if(rvCounter_q < i_vMaxCnt)
    begin
        rvCounter_d     =   rvCounter_q + 1'b1;
    end
    else
    begin
        rDone_d =   POL;    
    end
end
//////////////////////////////////////////////////////////////////////////////////
// Instances
//////////////////////////////////////////////////////////////////////////////////


//////////////////////////////////////////////////////////////////////////////////
endmodule
